Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/Silicon Labs/EFR32MG24A010F1536GM40/MODEM_S/SRC2NCOCTRL#0x0
No Description
Enable SRC2 NCO supplemental clock
Phase step per clock cycle
https://github.com/cmsis-svd/cmsis-svd-data